July 8, General Description. The converter fea-. The 8-channel multiplexer can direct-. The device eliminates the need for external zero and full-scale. Easy interfacing to microprocessors is provided.

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Be sure to consult the manufactures data-sheets for other chips. For a quick reference refer to table 2. Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals.

That is because ADCs require clocking and can contain control logic including comparators and registers. This means that in order to get it to work, there is a total of seven control signals that must be sent from the FPGA.

Table 2 provides a summary of all of the input and output to the chip. All of the signals are explained below. Address Lines Because the chip has an 8 channel multiplexer there are three address select lines: A, B, and C. C is the most significant bit and A is the least. See table 1 for details.

Once loaded the multiplexer sends the appropriate channel to the converter on the chip. The ALE should be pulsed for at least ns in order for the addresses to get loaded properly. As with all control signals it is required to have an input value of Vcc - 1. The following control signals are used to control the conversion. Clock The clock signal is required to cycle through the comparator stages to do the conversion.

There are 8, 8 clock cycle periods required in order to complete an entire conversion. This means that an entire conversion takes at least 64 clock cycles. Up to 72 if the start signal is received in the middle of an 8 clock cycle period.

The clock should conform to the same range as all other control signals. The maximum frequence of the clock is 1. The maximum clock frequency is affected by the source impedance of the analog inputs. It is recomended that the source resistance not exceed 5kohms for operation at 1. Start The purpose of the start signal is two fold. On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated.

Like the ALE pulse the minimum pulse width is ns. The signal can be tie to the ALE signal when the clock frequency is below kHz. At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins.

Note that it can take up to 2. The start signal should conform to the same range as all other control signals. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled.

In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA. The OE signal should conform to the same range as all the other control signals. The signal goes low once a conversion is initiated by the start signal and remains low until a conversion is complete.

Note : All control signals should have a high voltage from Vcc - 1. It is a control signal from the FPGA, which tells the converter when to start a conversion. It is a pulse of at least ns in width. Signal from the ADC. It goes low when a conversion is started and high at the end of a conversion.

Users can look for a rising edge transition. This is a bit of the digital converted output. Top rail of Reference voltage. The voltage level that, when received as an input, will output "" to the FPGA. Bottom rail of Reference voltage. Min Value Control signal from FPGA.

The minimum pulse width is ns. It can be tied to the Start line if the clock is operated under kHz. This is an address select line for the multiplexer.

It is the MSB of the select lines. It is the Second bit of the select lines. It is the LSB of the select lines. There are a couple of limitations that follow: The source resistance must be below 10kohms for operation below kHz and below 5kohms for operation around 1. The source must remain stable while it is being sampled and should contain little noise. This means it must remain stable for up to 72 clock cycles. If Vcc and ground are used as reference voltages, they should be isolated by decoupling with a 1 microF capacitor.

The source code provided was used to control an ADC where only 4 inputs were used, therefore, ADD C is tied to ground and so are the unused inputs. Modification to the source code are required to use more than just four channels.

Source code The source code consists of a few of files. The other files are enabled register, a register, and a multiplexer. You will also need to download multiplex. Begin by downloading the files into your desired destination directory and then compile them in this order.


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